(1) Field of the Invention
The invention relates to a Class-D Power Amplifier, and more particularly, to a Class-D Power Amplifier having a pulse coded digital input signal and typically using a two-level amplifier stage to drive an output load, like a loudspeaker.
(2) Description of the Prior Art
Class-AB amplifiers are notoriously inefficient and Class-D amplifiers overcome this shortfall. The common concept of Class D amplifiers is to switch the output between the 2 (or 3) output levels at a very high frequency—substantially higher than the highest audible frequency, which is done by feeding high-frequency pulses to the power amplification stage. Either the pulse-width ratio of the driving signal can be varied at a constant frequency or the pulse density of the driving signal can be varied at a constant pulse width in order to make the averaged (filtered) output signal follow the (amplified) input signal very closely. Such amplifier is referred to as Pulse Width Modulated (PWM) or as Pulse Density Modulated (PDM). The output voltage at the load, after passing a low pass filter, represents the input under the assumption of a constant supply voltage.
In the case of Pulse Density Modulation, the pulse width is always constant, where the high frequency pulses can be generated by for example a Sigma Delta Modulator. The output device, a Class-D driver, in the most common case can only drive +V or −V, thus limiting the pulse generation to 2 levels. An alternative Class-D driver can drive the output to +V, −V or zero, thus providing a maximum of 3 levels.
FIG. 1 shows a schematic block diagram of a state-of-the-art PDM Class-D Amplifier. It typically comprises a Sigma Delta Modulator (11) to generate the driving signal for the Class-D power output stage, which is typically an H-Bridge (12) and the output load, often a loudspeaker (13).
FIG. 2a shows a simplified diagram of a Complementary-Pair-Driver and FIG. 2b shows the 2 output signal levels and the corresponding states of the output devices. The output level at the load LOAD is “+V” with Transistor T1 closed, T2 open (21); it is “−V” with Transistor T2 closed, T1 open (22).
U.S. Pat. No. 6,311,046 (to Dent) describes a circuit with an input signal of varying amplitude and varying phase being converted into more than two signals of constant amplitude and controlled phase. Each of the more than two signals of constant amplitude and controlled phase is then separately amplified in separate amplifiers. The separately amplified more than two signals of constant amplitude and controlled phase are then combined to produce an output signal that is an amplification of the input signal at the desired power level. When converting the input signal into more than two signals, the phase of each of the more than two signals of constant amplitude and controlled phase is controlled to produce the output signal that is an amplification of the input signal at the desired power level. According to another aspect, a signal of varying amplitude and varying phase is generated from a plurality of constant amplitude varying phase signals, the sum of which is the signal of varying amplitude and varying phase.
U.S. Pat. No. 6,232,833 (to Pullen) shows a low jitter dead time circuit which uses one RC combination to set the turn on delay for both the upper and lower MOSFETs in the half bridge. This circuit minimized jitters in the turn on delay and results in matched turn on delays for both MOSFETs in a half bridge. This minimizes noise and distortion. This circuit is further designed to be used in conjunction with shunt regulators to reject ripple from the power supplies.